The present invention relates to a semiconductor device for carrying out high-speed switching with a low power supply voltage, in particular to a semiconductor device suitable to a power supply voltage of 1V or less.
Hitherto, an inverter having a MISFET has been widely used as one of logic circuits. As shown FIG. 1, in this inverter an n (channel)-type MISFET 4 and a p (channel)-type MISFET 5 are connected in series between a power supply terminal (V.sub.DD) and a ground terminal (0V). A source or a drain of the MISFET 4 is coupled to a source or a drain of the MISFET 5 so that the coupling portion constitutes an output terminal of the inverter, and a gate of the MISFET 4 and a gate of the MISFET 5 are commonly coupled to form an input terminal 6 of the inverter.
When a power supply voltage is referred to as V.sub.DD in such an inverter having the MISFET as shown in FIG. 1, a consumed electric power is in proportion to V.sub.DD.sup.2. When a gate insulation film is attempted to be made thinner for higher-speed switching under a condition that the source voltage V.sub.DD is kept high, an electric field which is applied to the gate insulation film increases to cause an electric field-breakdown of the gate, a rise in a leakage current in the gate, and a poor dielectric breakdown voltage. Therefore, it is known that it is useful for reducing consumed electric power and improving reliability to lower a power supply voltage under the condition that the gate voltage is kept constant.
The delay time .tau..sub.pd in such a static inverter as shown in FIG. 1 is as follows: EQU .tau..sub.pd =kC.sub.L V.sub.DD /(V.sub.DD -V.sub.th).sup.h
wherein C.sub.L represents the load capacitance of the next stage at the inverter, V.sub.th represents the threshold voltage of a p-type MISFET and an n-type MISFET, k is a proportional constant, and n is from 1 to 2. The voltage at an input terminal 6 of the inverter changes from 0 to V.sub.DD. Thus, in a low power supply voltage in which the V.sub.DD is, for example, 1V or less, the difference between the threshold voltage V.sub.th and the power supply voltage V.sub.DD is reduced so that the .tau..sub.pd increases, thereby making a high-speed operation difficult.
In a CMOS circuit, active researches have been made on reduction of a power supply voltage resulting in reduction of an electric power to be consumed. It is necessary for a low voltage-operation without degradation in operation speed that the threshold voltage V.sub.th is reduced. However, if the V.sub.th is reduced too much, it is impossible to satisfactorily cut off the subthreshold electric current penetrating through the source and drain electrodes of the transistor. In applications by use of a voltage which is not more than a built-in potential of a pn-junction of Si, it is known that such a circuit as shown in e.g., FIG. 2 is effective for obtaining a good cut-off characteristic. (F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu., IEDM, Technical Digest, 809, (1994)). The circuit shown in FIG. 2 will be described briefly.
In FIG. 2, each of gates of transistors Q1 and Q2 is electrically connected to a substrate or a body electrode. In the specification, this structure is referred to as GST (Gate-Substrate Tie). The Q1 and the Q2 have a p-channel type MISFET and an n-channel type MISFET, respectively, and they constitute a CMOS inverter.
In the Q2 structure shown in FIG. 2, when a positive voltage V.sub.DD is applied to the gate, the positive voltage is also applied to the substrate. Accordingly, a threshold voltage is reduced to a lower level by a substrate bias effect than in the case in which the substrate voltage is kept 0V, so that electric current drivability of Q2 is raised. When the gate voltage is 0V, the substrate bias voltage is also kept 0V. This causes the same leakage current as in the case that the substrate bias voltage is kept 0V, so that the ON/OFF ratio is improved over the circuit in which its substrate bias voltage is kept constant.
However, in the present circuit, the leakage current during standby state is determined in the case in which the substrate voltage is set to 0V. The substrate bias voltage during standby state is closer to the substrate bias voltage during active state than, for example, a circuit in which the substrate voltage is V.sub.DD during active state and the substrate voltage is less than 0V, i.e., a negative during standby state, so that the increase of the threshold voltage by a substrate bias effect is smaller and the leakage current from a current penetrating through the source and the drain during standby state increases more.
As shown in FIG. 3, in a circuit in which the inverters as shown in FIG. 2 are connected in series, the leakage current during standby state may cause another problem. In the circuit shown in FIG. 3, an output terminal of the first inverter having transistors Q1 and Q2 is connected in series to an input terminal of the second inverter having transistors Q3 and Q4 to form a node. The Q1 and Q3 have p-channel type MISFETs and the Q2 and Q4 have n-channel type MOSFETs. They all constitute CMOS inverters.
When the voltage at an input node 101' of the first inverter is set up to a higher voltage than the logic inversion voltage, e.g., to V.sub.DD, the voltage at an input node 112 of the second inverter is about 0V. In this case, the transistor Q3 is having a p-type MISFET, so that the pn-junction of the Q3 between a node 106' connected to a power supply for the power supply voltage V.sub.DD and a substrate electrode 102 is forward-biased. Thus, a forward diode current flows. At that time, in the Q2 transistor its gate and substrate electrode are positively biased, and the threshold voltage is low, and Q2 is turned on. As a result, the forward diode current, which is a direct current, from the Q3 flows through the Q2 to a ground voltage node 106. The passage of this current is shown an arrow of a solid line in FIG. 3. On the contrary, when the voltage at a node 101' is lower than the inversion voltage, a similar penetration current flows through the transistors Q4 and Q1.
In this circuit, the leakage current during standby state is also determined in the case the substrate voltage is set to 0V. The leakage current during standby state is larger than, for example, a circuit in which the substrate voltage during active state is V.sub.DD and one during standby state is negative.
As described above, if a gate insulation film is attempted to be made thinner in prior logic circuits such as an inverter of MISFETs in order to realize a high-speed operation, the electric field applied to the gate insulation film increases to cause dielectric breakdown of the gate and increase a leakage current. Reduction in the substrate voltage V.sub.DD also causes increase in delay time .tau..sub.pd. In short, in any logic circuit in which its threshold voltage is kept constant, it is difficult to reduce delay time .tau..sub.pd with the reduction in the substrate voltage V.sub.DD. In any logic circuit in which there is used only a GST transistor wherein a gate is connected to a substrate, it is also difficult to make penetration current during standby state small under a condition that electric current drivability during active state is kept.